Of the many applications for serial to parallel and parallel to serial converters their utilisation in telecommunication switches is of ever increasing interest due to the growth in traffic and the need to provide adequate capacity for the diversity of links in demand.
Telecommunication switches switch between logical channels capable of carrying serialised data and conventionally comprise a number of serial input and output channels. They often also incorporate serial to parallel conversion for enabling parallel processing and routing of the payload data, followed by reconversion of the parallel data to serial data streams while routing these onto the correct output channels.
Examples of a serial to parallel converter and a parallel to serial converter are described in U.S. Pat. No. 5,475,680 to Turner for use in an asynchronous time division multiplexed (ATDM) switching system. In the serial to parallel converter, half the data packets from each incoming serial channel are buffered in one of two shift registers. Data is shifted into each of the shift registers synchronously. This is made possible by disposing a phase aligner upstream of the converter to align the incoming packets. Once the first of these registers is full, the second half of the data packet is read into the second shift register and, at the same time, data is read out in parallel from the first shift registers of each channel in sequence. The two packet halves are subsequently stored separately while being processed. The resulting arrangement is relatively complex both in terms of its structure and its operation control.
A further form of serial to parallel converter described in U.S. Pat. No. 5,463,630 to Tooher and used for time division multiplexing and demultiplexing serial data streams utilises a structure of dual port random access memory (RAM) cells. One such structure dimensioned to hold one 64-bit data word is associated with each serial channel. Serial access to the structure is obtained via a shift register or by sequentially addressing the RAM cells. In the serial to parallel converter a serial driver is disposed between the incoming channel and the structure. A disadvantage of this arrangement is that the relative timing between input and output of storage structure is very complicated, and in the worst case may preclude a serial to parallel converter from being used at full capacity. This overall arrangement is also of a relatively complex structure and is inflexible in terms of the possible application of the converters.
It is accordingly an object of the present invention to overcome the disadvantages of prior art arrangements.
It is a further object of the present invention to provide serial to parallel converters and parallel to serial converters that are of simple structure and are flexible in terms of configuration, enabling their utilisation in a variety of applications.